Several techniques of designing adder units for performing high speed additions of decimal operands consisting of a plurality of decimal digits are disclosed by Schmookler and Weinberger in "High Speed Decimal Addition", IEEE Transactions on Computers, Volume 20, No. 8, August 1971, pages 862-866. These techniques provide a direct production of decimal sums without the need of first producing the binary sums, and they avoid the decimal correction of the result in an additional operation cycle by adding six to each sum digit where a carry is produced. The techniques use carry generate and propagate functions for the decimal digits to perform a carry look ahead function over the digit positions and for the direct production of the decimal sum digits.
A combined binary/decimal adder unit using a carry look ahead logic through a plurality of decimal digit positions and a direct production of the decimal sum digits is disclosed in the U.S. patent application Ser. No. 969.244, Haller et al, "Combined Binary/Decimal Adder Unit". In this unit pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.
The time critical path of the add and subtract operations resides in the highest decimal digit position for which the carry-in signal is generated at the end of the carry processing operation. Re-corrections of the sums and differences by -6 corrections would require an additional operation delay which limits cycle rate of the processor unit in which the decimal additions and subtractions have to be performed. The previous unit avoids such additional operation delay but still requires some circuit level delay for the selection of the pre-sum selection.